Pipeline processor and computer system and apparatus and method for executing pipeline storage instructions using a single cache access pipe stage

摘要

The present invention is directed to a mechanism for executing a store instruction such that a single cache access stage is required. Since the load instruction requires a single cache access stage where cache reads occur, both the store and load instructions of the present invention use multiple uniform cache access stages. If there is a tag hit for storage, the save instruction is executed in the pipeline microprocessor so that the cache memory is read during the pipeline stage of a given store instruction and an immediate decision is made. Assuming there is a cache hit, cache writes associated with a given store instruction are performed during the same pipeline stage as the cache access stage of a subsequent instruction that does not write to the cache, or if no instruction exists. For example, cache data writes occur for a given store concurrent with the read of the cache tag of subsequent store instructions. This results in a more uniform and efficient pipeline format for each instruction. During a period where a given storage is delayed, the data is placed in a storage buffer. For cache misses, when a data line is returned from memory, the storage buffer determines the free period of the cache and stores the data. The storage mechanism is implemented in a pipeline processor and also by a general purpose computer system.