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METHOD OF DESIGNING A CMOS LOGIC CIRCUIT
METHOD OF DESIGNING A CMOS LOGIC CIRCUIT
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机译:CMOS逻辑电路的设计方法
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摘要
In the present invention, a logic circuit is divided into a first logic circuit and a second logic circuit, a standby circuit is interposed between the first logic circuit and the second logic circuit, and a transistor structure of a cell in the first logic circuit or the second logic circuit. Provides a method of designing a CMOS logic circuit characterized by the conversion. In addition, the present invention provides a method for receiving, as an input, circuit information described at the transistor level, preset signal information, information necessary for logic synthesis, and cell information formed by a transistor having a high and low threshold value as cell inputs for realizing logic synthesis. Means and an internal signal calculating means for calculating signal values of each node of the logic circuit using preset information and cell substitution in the circuit, wherein the cell replacement system is characterized. In addition, the present invention is the logic circuit information and the predetermined signal information is input to calculate the signal value of each node of the logic circuit based on the preset signal information, furthermore, the calculated internal signal value, logic circuit information and high ... Cell information in which a cell formed of a low threshold transistor is registered is inputted to output new logic circuit information through replacement of a cell in the logic circuit, and new logic circuit information is output by replacement of a cell in the circuit having the characteristic. It provides a cell replacement method. In addition, the present invention provides the circuit information described at the transistor level, preset signal information, information necessary for logic synthesis, and cell information in which a cell formed of a transistor having a high and low threshold value is registered, and information for which the cell is replaced with a circuit. Provided is a recording medium in which a cell replacement program is inputted to realize internal signal calculation so as to calculate a signal value of each node of a logic circuit based on the above, and outputs logic circuit information through substitution in the circuit having the characteristics.
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