首页> 外国专利> THREE-VALUED LOGIC SYSTEM LOGIC CIRCUIT DESIGNING APPARATUS, THREE-VALUED LOGIC SYSTEM LOGIC CIRCUIT DESIGNING METHOD, AND THREE-VALUED LOGIC SYSTEM LOGIC CIRCUIT DESIGNING PROGRAM

THREE-VALUED LOGIC SYSTEM LOGIC CIRCUIT DESIGNING APPARATUS, THREE-VALUED LOGIC SYSTEM LOGIC CIRCUIT DESIGNING METHOD, AND THREE-VALUED LOGIC SYSTEM LOGIC CIRCUIT DESIGNING PROGRAM

机译:三值逻辑系统逻辑电路设计装置,三值逻辑系统逻辑电路设计方法和三值逻辑系统逻辑电路设计程序

摘要

PROBLEM TO BE SOLVED: To easily and rapidly design a gate structure of a three-valued logic system.;SOLUTION: A three-valued logic system logic circuit designing apparatus for supporting the designing of a logic circuit of a three-valued logic system includes an input part 2 for accepting the inputs of various information; and a logic circuit generating process part 7 for referring to function selection rules using the information accepted by the input part 2, and based on the kind of a standard shape and the kind of a cross section, so as to create a standard shape expansion chart for specifying the logic circuit that corresponds to a 1-output operation table.;COPYRIGHT: (C)2006,JPO&NCIPI
机译:解决的问题:为了容易且快速地设计三值逻辑系统的门结构。解决方案:支持三值逻辑系统的逻辑电路设计的三值逻辑系统逻辑电路设计装置包括:输入部分2,用于接受各种信息的输入;逻辑电路生成处理部7,其使用输入部2接受的信息并根据标准形状的种类和截面的种类,参照功能选择规则,制作标准形状的展开图。用于指定与1输出操作表相对应的逻辑电路。;版权:(C)2006,JPO&NCIPI

著录项

  • 公开/公告号JP2006113695A

    专利类型

  • 公开/公告日2006-04-27

    原文格式PDF

  • 申请/专利权人 NAKAMURA KAZUTO;

    申请/专利号JP20040298253

  • 发明设计人 NAKAMURA KAZUTO;

    申请日2004-10-12

  • 分类号G06F17/50;H03K19/20;

  • 国家 JP

  • 入库时间 2022-08-21 21:51:40

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