Delay locked loop circuit including coarse lock control circuit for controlling accurate coarse lock and coarse lock control method thereof

摘要

PURPOSE: A circuit and a method for controlling a coarse lock for an exact coarse locking and a delay locked loop circuit having the coarse lock control circuit are provided to improve the accuracy of the coarse locking by sampling an input clock signal and an output signal. CONSTITUTION: A first sampling circuit(61) samples an output signal of an n-th unit delayer out of unit delayers in response to an input clock signal of a delay locked loop circuit. The n is an integer. A second sampling circuit(62) samples an output signal of n+1th unit delayer out of the unit delayers in response to an input clock signal of the delay locked loop circuit. A third sampling circuit(63) samples the input clock signal of the delay locked loop circuit in response to the output signal of the nth unit delayer. A fourth sampling circuit(64) samples the input clock signal of the delay locked loop circuit in response to the output signal of the n+1th unit delayer.