首页> 外国专利> Gate contact formation method in deep trench based DRAM integrated circuit fabrication, involves forming bit line, substrate and gate contact openings on substrate using plasma doping

Gate contact formation method in deep trench based DRAM integrated circuit fabrication, involves forming bit line, substrate and gate contact openings on substrate using plasma doping

机译:基于深沟槽的DRAM集成电路制造中的栅极接触形成方法,涉及使用等离子体掺杂在衬底上形成位线,衬底和栅极接触开口

摘要

The array and periphery areas of a substrate (10) are concurrently etched to form bit line contact openings and substrate contact openings respectively using plasma doping. A dielectric layer covering semiconductor device structure provided on the substrate, is etched to form a gate contact opening. A conducting layer is filled into the openings so as to form contacts.
机译:使用等离子体掺杂同时蚀刻衬底(10)的阵列和外围区域以分别形成位线接触开口和衬底接触开口。蚀刻覆盖设置在基板上的半导体器件结构的介电层,以形成栅极接触开口。导电层填充到开口中以形成接触。

著录项

  • 公开/公告号DE10145173A1

    专利类型

  • 公开/公告日2003-04-10

    原文格式PDF

  • 申请/专利权人 PROMOS TECHNOLOGIES INC.;

    申请/专利号DE2001145173

  • 发明设计人 LEE BRIAN;

    申请日2001-09-13

  • 分类号H01L21/8242;

  • 国家 DE

  • 入库时间 2022-08-21 23:42:40

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