Method for accessing scan chains and updating an EEPROM-resident FPGA code by a system management processor and a JTAG bus

摘要

A method for updating a programmable device configuration code that is stored in a system's EEPROMs is operable on complex systems with separate management and system processors. The method includes executing a sequence to update a programmable device configuration code on a system management processor including the steps of erasing the EEPROMs, writing at least one block of configuration code to the EEPROMS, and checking for errors after writing. The errors searched for in the test include a failure of a FIFO with respect to a void. After detecting the errors, the method includes an automatic retry of the write. The exemplary embodiments of the method can be operated on systems which have a number of serial buses which connect the EEPROMs to a common configuration logic and on systems which have a number of management processors, each of which can access the common configuration logic.