首页> 外国专利> Test system for integrated circuit chips has a sealing arrangement that attaches to the lower side of the test circuit board to prevent damage or interference due to frost during low temperature testing

Test system for integrated circuit chips has a sealing arrangement that attaches to the lower side of the test circuit board to prevent damage or interference due to frost during low temperature testing

机译:用于集成电路芯片的测试系统具有密封装置,该密封装置附着在测试电路板的下侧,以防止在低温测试过程中由于霜冻而造成损坏或干扰

摘要

Test system for integrated circuit chips has a test circuit board (130), a temperature control unit (120) and a test unit (110), suitable for determination of the properties of a number of integrated circuit chips. The chips under test are placed on the upper surface of the test circuit board. A sealing unit (140) is brought into contact with the second lower surface of the test circuit board to isolate at least a part of it against the surrounding air.
机译:用于集成电路芯片的测试系统具有测试电路板(130),温度控制单元(120)和测试单元(110),其适于确定多个集成电路芯片的特性。被测芯片放置在测试电路板的上表面。使密封单元(140)与测试电路板的第二下表面接触,以将其至少一部分与周围空气隔离。

著录项

  • 公开/公告号DE10300535A1

    专利类型

  • 公开/公告日2003-07-24

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号DE2003100535

  • 发明设计人 KIM KI-YEUL;KIM YOON-MIN;

    申请日2003-01-07

  • 分类号G01R31/28;

  • 国家 DE

  • 入库时间 2022-08-21 23:41:49

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