Logic synthesis method for the design of semiconductor integrated circuits

摘要

A method for designing a semiconductor integrated circuit having a plurality of combinational circuits each of which includes a signal propagation path and having registers which are provided at stages respectively preceding and succeeding at least one of said plurality of combinational circuits, said method comprising: a first step of mapping, when there exists a combinational circuit in said plural combinational circuits of which signal propagation path has a signal propagation delay not more than a design delay upper limit, said combinational circuit into a combinational circuit of a first type driven by a low voltage from a low-voltage source; a second step of mapping, when there exists a combinational circuit in said plural combinational circuits of which signal propagation path has a signal propagation delay above the design delay upper limit, said combinational circuit into a combinational circuit of a second type driven by a high voltage from a high-voltage source; a third step of mapping each said register into a register driven by a low voltage from said low-voltage source. IMAGE