The small amplitude logic circuit and the small amplitude latched circuit null which applies this technology

摘要

PURPOSE: To improve a margin at the time of low voltage by providing this small amplitude logic circuit with plural differential amplifier circuits(DACs) including transistors(TRs) and connecting the output terminal of the 1st DAC to a terminal connected to the 2nd DAC. ;CONSTITUTION: The small amplitude logic circuit 10 inputs complementary small amplitude signals A, B and outputs an output similar to that from a NAND circuit to an output terminal, the inverse of (A.B). The circuit 10 is constituted of an DAC consisting of a pair of source-connected PMOSs 2-1, 2-2 and a DAC consisting of a pair of source-connected NMOSs 2-3, 2-4. When both the input signals A, B are a high level, currents flowing into the PMOS 2-1 and the NMOS 2-3 connecting their gates to an input terminal are reduced. Thereby the potential of a node ϕ2-2 is reduced, the level of a node ϕ2-1 is turned to a low level and an output is generated from an output terminal. When the signals A, B are combined at the high or low level, a high or low output is generated from the output terminal.;COPYRIGHT: (C)1996,JPO