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Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features
Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features
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机译:使用不规则形状的导电填充物特征来改善导电层的平面化,同时减少填充物特征引入的寄生电容
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摘要
A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduce capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.
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