首页> 外国专利> SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE PROCESS OF MANUFACTURING THE SAME HAVING POLY-SILICON PLUG, WIRING TRENCHES AND BIT LINES FORMED IN THE WIRING TRENCHES HAVING A WIDTH FINER THAN A PREDETERMINED SIZE

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE PROCESS OF MANUFACTURING THE SAME HAVING POLY-SILICON PLUG, WIRING TRENCHES AND BIT LINES FORMED IN THE WIRING TRENCHES HAVING A WIDTH FINER THAN A PREDETERMINED SIZE

机译:半导体集成电路设备及其制造工艺,该工艺具有多晶硅塞,接线槽和线槽中形成的位线,其宽度超过预定尺寸

摘要

A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
机译:通过使位线的宽度比由光刻的分辨率的极限确定的最小尺寸更细,来减小DRAM的存储单元的尺寸。通过在形成于氧化硅膜中的布线沟槽的内壁上形成氧化硅膜并通过在氧化硅膜内部形成位线来使位线细化。沉积形成在沟槽中的氧化硅膜,使得该氧化硅膜的厚度薄于布线沟槽的宽度的一半,并且在该氧化硅膜内部的微小间隙中埋入金属膜以作为钻头的材料线。

著录项

  • 公开/公告号US6762449B2

    专利类型

  • 公开/公告日2004-07-13

    原文格式PDF

  • 申请/专利权人 HITACHI LTD.;

    申请/专利号US20000548966

  • 申请日2000-04-13

  • 分类号H01L271/08;H01L297/60;

  • 国家 US

  • 入库时间 2022-08-21 23:19:01

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