首页> 外国专利> Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor

Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor

机译:串扰分析方法,使用该方法设计/制造电子电路装置的方法及其电子电路库的记录介质

摘要

This is a method for more accurately calculating delay times in an electronic circuit device wherein signal arrival times on a victim wire and a plurality of aggressor wires adjacent thereto dynamically vary dependent on an input signal pattern by analyzing values of crosstalk-deriving delay degradation occurring between those wires. By utilizing delay degradation information searchable according to relative signal arrival times between the victim wire and the aggressor wires and adding delay degradations arising between the victim wire and the aggressor wires, calculated at every signal arrival time on the victim wire, the total delay degradation in the presence of a plurality of aggressor wires is calculated. Designing of a high-speed and large-scale electronic circuit device is facilitated and, because a superfluous margin regarding delay times can be eliminated, such electronic circuit devices can be efficiently designed and manufactured.
机译:这是一种用于更精确地计算电子电路装置中的延迟时间的方法,其中,通过分析在两根导线之间产生的串扰引起的延迟降低的值,信号在受害导线和与其相邻的多条侵扰导线上的到达时间根据输入信号模式而动态变化。这些电线。通过利用可根据受害导线和侵害导线之间的相对信号到达时间搜索的延迟退化信息,并添加在受害导线和侵害导线之间产生的延迟降级(在受害导线上的每个信号到达时间计算),总延迟降低为计算多条攻击线的存在。便利了大规模的高速电子电路装置的设计,并且由于可以消除关于延迟时间的多余余量,因此可以有效地设计和制造这种电子电路装置。

著录项

  • 公开/公告号US6772403B1

    专利类型

  • 公开/公告日2004-08-03

    原文格式PDF

  • 申请/专利权人 HITACHI LTD.;

    申请/专利号US20020257674

  • 发明设计人 YASUHIKO SASAKI;

    申请日2002-10-15

  • 分类号G06F175/00;

  • 国家 US

  • 入库时间 2022-08-21 23:16:56

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