Cache-tag control method in information processing apparatus having cache, with error checking mechanism in cache tag, and information processing apparatus using this control method

摘要

To provide a cache-tag control method capable of correcting an error and capable of keeping a high-speed operation of a system at the same time. A true-tag with a parity code attached and a shadow-tag having an inverted polarity of the true-tag are stored respectively in separate addresses within a cache tag-RAM. At the time of retrieving the tags, both the true-tag and the shadow-tag are checked respectively to see whether there is an error in each tag. When an error has been detected, a hit decision is made by using a tag in which there is no error. Further, data within the cache tag-RAM is updated by using the tag in which there is no error, thereby correcting the error.