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Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices

机译:用于绝缘体上硅(SOI)器件实现掩埋双轨配电和集成去耦电容的方法和半导体结构

摘要

Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers. A connection to the first intermediate silicon layer is formed without making electrical connection to the second intermediate silicon layer.
机译:提供了用于实现绝缘体上硅(SOI)器件的掩埋双轨功率分配和集成去耦电容的方法和半导体结构。提供了体硅衬底层,其限定了一个配电轨。进行高能深氧注入以产生深掩埋氧化物层和第一中间硅层。深埋氧化物层设置在体硅衬底层和第一中间硅层之间。第一中间硅层限定另一配电轨。执行较低能量的氧注入以产生浅埋入氧化物层和第二中间硅层。浅埋氧化物层设置在第一中间硅层和第二中间硅层之间。形成到块状硅衬底层的连接而没有到中间硅层的电连接。形成到第一中间硅层的连接而没有电连接到第二中间硅层。

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