Phase locked loop circuit having a wide oscillation frequency range for reducing jitter

摘要

A PLL circuit having a wide oscillation frequency range for reducing a jitter. The PLL circuit including a phase comparator for generating a phase difference signal by comparing a phase of a reference signal with a phase of a comparison signal. An oscillator generates an oscillation frequency signal having an oscillation frequency according to a control signal having a current corresponding to the phase difference signal. A detection circuit generates a detection signal by detecting the current of the control signal. A signal generation circuit generates a signal for changing the oscillation frequency of the oscillator such that the current of the control signal is within a predetermined range in accordance with the detection signal.