A wide lock-range, low jitter phase-locked loop for multi-standard SerDes application

摘要

A 0.8–3.6GHz Phase-locked loop (PLL) with quadrature outputs for multi-standard SerDes application is presented in this paper. To reach wide range output frequency, the lower output range is implemented by a divide-by-two operation on the upper output which is generated from a two-stage quadrant ring-VCO. Further more, adaptive bandwidth technique is applied to guarantee the stability of the loop. In addition, the process-dependent charge pump current mirrored from high precision bandgap reference circuit is used to cancel the bandwidth fluctuation from the process variation. The PLL is implemented in a 130nm digital CMOS process, while the core occupies 0.1mm² and draws 5.1mA to 7.5mA current from 1.2V supply without yielding RMS jitter performance which is about 2.0ps.