Packet transfer apparatus which generates access reject command during a DMA transfer

摘要

A packet transfer apparatus for transferring data packets between devices connected to a bus includes a receiving circuit connected to the bus for receiving a packet from the bus and a transmit circuit, also connected to the bus, for forming and placing a transmit packet on the bus. A header identification circuit, connected to the receiving circuit, detects a packet header of the received packet and determines if the packet header indicates a DMA transfer operation. A first buffer is provided for storing the packet data when the packet header indicates a DMA transfer and a second buffer is provided for storing the packet data when the packet header does not indicate a DMA transfer. A memory is connected to the first buffer and stores the packet data it receives from the first buffer. The memory also transfers stored data to the first buffer. A DMA controller is provided to control a DMA operation between the memory and the first buffer. A processor handles non-DMA operations and is free to perform such operations while a DMA operation is being performed. That is, when a DMA operation is being carried out by the memory and the first buffer, the processor is able to respond to a request from an external device using the transmit circuit.