Serial-link circuit including capacitive offset adjustment of a high-speed receiver

摘要

A serial link circuit includes a transmitter which multiplexes the circuit's input signals together and uses a single processing circuit to generate a multiplexed output to be transmitted. The multiplexing is done with a limited voltage swing prior to preamplification. In this way, clock loading (and hence clock buffer area), power and jitter are significantly reduced. The complementary link receiver includes a demultiplexer implemented with sense amplifiers that are digitally unbalanced using trimmer capacitors to cancel the receiver's offset voltage. This allows the receiver to be implemented using very small elements to save power, and enables the link to operate reliably with a very low signal swing.