Correction of layout pattern data during semiconductor patterning process

摘要

A layout pattern data correction device includes: (a) edge extracting means for extracting a first target edge to be corrected from an original layout pattern of a circuit; (b) edge modifying region setting means for setting an edge modifying region in which the first target edge is modified with a predetermined point in the first target edge taken as a center; (c) edge modifying means for modifying the first target edge within the edge modifying region into a second target edge to be corrected; (d) corrected pattern forming means for forming a corrected pattern based on the second target edge; and (e) boolean operation means for performing a predetermined boolean operation based on both of the original layout pattern and the corrected pattern.