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Non volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values

机译:非易失性存储器单元感测电路,特别适用于低电源电压和高容性负载值

摘要

The present invention relates to a sensing circuit (10, 100) for a memory cell (11) inserted between a first (Vdd) and a second voltage reference (GND) and connected, in correspondence with a first inner circuit node (XBL), to the memory cell (11) of the type comprising:a first bias current (Ip) generator (12) inserted between the first voltage reference (Vdd) and the first inner circuit node (XBL);a comparator (17) having a first input terminal (-) connected to a comparison circuit node (Xrif), connected in turn to the first voltage reference (Vdd) by means of at least a second reference current (Iref) generator (15), as well as a second input terminal (+) connected to a circuit node (Xmat) connected in turn to the first inner circuit node (XBL), an output terminal (OUT) of the comparator (17) corresponding to an output terminal of the sensing circuit (10).;Advantageously according to the invention, the sensing circuit comprises also:a cascode-configured bias circuit (13) inserted between the inner circuit node (XBL) and the matching circuit node (Xmat) and connected to a third voltage reference (Vref); anda current/voltage conversion stage (16) connected to the matching circuit node (Xmat) and to the comparison circuit node (Xrif), as well as to the second voltage reference (GND).
机译:本发明涉及一种用于存储单元(11)的感测电路(10、100),其插入在第一(Vdd)和第二参考电压(GND)之间并与第一内部电路节点(XBL)相对应地连接,包括以下类型的存储单元(11): 插入在第一参考电压(Vdd)与第一内部电路节点(XBL)之间的第一偏置电流(Ip)生成器(12); 比较器(17),其具有连接到比较电路节点(Xrif)的第一输入端子(-),该输入端子通过至少第二参考电流(Iref)生成器又连接到第一参考电压(Vdd) (15),以及依次连接到第一内部电路节点(XBL)的电路节点(Xmat)的第二输入端子(+),比较器(17)的输出端子(OUT)对应于 ;有利地,根据本发明,该传感电路还包括:级联配置的偏置电路(13)插入内部电路节点(XBL)和匹配电路节点(Xmat)之间,并连接到第三参考电压(Vref);电流/电压转换级(16),其连接到匹配电路节点(Xmat)和比较电路节点(Xrif),以及第二参考电压(GND)。

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