Bus architecture with primary bus and secondary bus for microprocessor systems

摘要

A microprocessor system comprising a high speed primary bus (AHB) controllable by more than one master device connected to it and at least a secondary bus (APB) coupled to the primary bus (AHB) through an interface (SLAVE WRAPPER) and to which may be connected relatively slow peripherals, includes in said interface (SLAVE WRAPPER) coupling said secondary bus (APB) to said high speed primary bus (AHB) a dedicated direct memory access controller (DMA) that during each data transfer routine between a peripheral connected to said secondary bus and a peripheral connected to said primary bus reduces the engagement of the primary bus to a single transfer phase.;Moreover, even all the interfaces (SLAVE WRAPPER) for coupling memory devices (RAM, FLASH) and other fast peripherals to the primary high speed bus (AHB) may includes a dedicated direct memory access controller (DMA) thus reducing to a single transfer phase engagement of said high speed bus (AHB) during a data transfer routine among memory devices (RAM, FLASH) and fast peripherals connected to the high speed primary bus.