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Mask for highly integrated circuit device fabrication generating method of their layout fabrication method thereof and fabrication method for highly integrated circuit using the same
Mask for highly integrated circuit device fabrication generating method of their layout fabrication method thereof and fabrication method for highly integrated circuit using the same
PURPOSE: A mask for manufacturing a high integrated circuit, a layout forming method thereof, a manufacturing method thereof, and a method for manufacturing a high integrated circuit device using the same are provided to be capable of minimizing total line width of a metal line of the high integrated circuit device. CONSTITUTION: A mask set for manufacturing a high integrated circuit is provided with a pair of phase shift regions for defining an access metal line and an alternate type phase shift mask(20) formed at the upper portion of a transparent substrate for defining the pair of phase shift region. At this time, the alternate type phase shift mask includes the first opaque pattern. The mask set further includes the second opaque pattern formed at the upper portion of the transparent substrate for preventing the access metal line from being erased and a half tone phase shift trim mask(30) for defining a pass metal line connected with the access metal line.
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