Semiconductor memory device including means for internally controlling most significant bit of address using mode register set

摘要

PURPOSE: A semiconductor memory device having a unit for controlling internally a most significant bit of an address by using a mode register set is provided to reduce the testing time by controlling internally the most significant bit of the address without allocating all bits of the address to a channel of a testing equipment. CONSTITUTION: A first inverter(41) inverts a most significant bit(TMSB) of an address applied from an outside. A first NOR gate(42) receives a first mode output signal(MRS-A) of a mode register set and an output signal of the first inverter(41). A second NOR gate(43) receives a second mode output signal(MRS-B) of the mode register set and an output signal of the first NOR gate(42). A second inverter(44) inverts an output signal of the second NOR gate(43) to generate a most internal significant bit(INTMSB).