Delay locked loop capable of compensating the delay of internal clock signal according to the variation of output driver strength in semiconductor memory device

摘要

PURPOSE: A delay locked loop of a semiconductor memory device is provided which can compensate delay of an internal clock signal according to driving power variation of an output driver which can track the delay of the internal clock signal accurately according to the impedance variation of the output driver. CONSTITUTION: A replica output driver(117) has the same delay as an internal clock signal generated in an output driver whose driving power is varying. A phase detector(113) detects a phase difference between the internal clock signal delayed through the replica output driver and an external clock signal. A control circuit(115) generates a control signal in response to an output signal of the phase detector. And a variable delay circuit(111) generates the internal clock signal synchronized to the external clock signal by delaying the external clock signal, in response to the control signal.