METHOD FOR MANUFACTURING FLAT CELL PRODUCTS TO REDUCE TAT(TOTAL AROUND TIME)

摘要

Purpose: a kind of method is arranged to reduce TAT (around the time all) for manufacturing flat cell product by simplifying manufacturing process. Construction: a n traps (112) and a p-well (114) are formed in semi-conductive substrate (100), are defined with a logical gate (LP) and a flat cell part (FP). E1 ion implantings are performed in order to the starting voltage of one parts NMOS of control. E2 processing will carry out p-well to control the starting voltage of the parts PMOS. E2 ion implantings are performed. Then, the ion implanting of a blank will be combined structure.