INTEGRATED CIRCUIT PROVIDED WITH MEMORY CELL ARRAY CAPABLE OF PERFORMING READ OPERATION AND WRITE OPERATION SIMULTANEOUSLY, IN WHICH THE PERIOD OF A CLOCK SIGNAL IS REDUCED

摘要

PURPOSE: An integrated circuit provided with a memory cell array capable of performing a read operation and a write operation simultaneously is provided to shorten the period of the clock signal by performing the read operation and the write operation during one period at the same time. CONSTITUTION: An integrated circuit(200) provided with a memory cell array capable of performing a read operation and a write operation simultaneously includes a plurality of memory blocks(SMB1-SMBM), a plurality of data memory blocks(DMB1-DMB4) and a tag memory controller(210). Each of the memory blocks(SMB1-SMBM) is provided with a plurality of sub-memory blocks. Each of the data memory blocks(DMB1-DMB4) corresponds to the memory blocks(SMB1-SMBM). The tag memory controller(210) writes/reads the data in/from the memory blocks(SMB1-SMBM) and the data memory blocks(DMB1-DMB4) in response to the write address or the read address. And, each of the sub-memory blocks does not access to the same sub-memory block at the same time although the write address and the read address simultaneously inputted are equal to each other.