METHOD FOR FORMING CAPACITOR OF LOGIC SEMICONDUCTOR DEVICE TO MINIMIZE VARIATION OF CAPACITANCE USING THREE-STEP ANNEALING PROCESSES

摘要

PURPOSE: A method for forming a capacitor of a logic semiconductor device is provided to minimize the variation of capacitance by using three-time annealing processes. CONSTITUTION: A first planarized insulating layer(19) is formed on a substrate(11) having a word line(17). A first metal line(25) is formed to connect the word line and the substrate. The resultant structure is firstly annealed. A second planarized insulating layer is formed between the first metal lines. A dielectric film is formed on the resultant structure. The resultant structure is secondly annealed. A second metal line is formed on the dielectric film. The resultant structure is thirdly annealed. By patterning the second metal line, upper and lower electrodes for a capacitor are formed.