Clock signal pulse ratio correction device for semiconductor memory compares pulse ratio of corrected clock signal and corrected complementary clock signal with required pulse ratio for adjustment of correction delay

摘要

The pulse ratio correction device has a pulse ratio adjustment device receiving the clock signal to be corrected and a complementary clock signal, each fed to a delay device with a variable delay, for providing a clock signal with a corrected pulse ratio and a complementary clock signal with a corrected pulse ratio. The delay of each delay device is controlled by a correction signal provided by a device for determination of the actual pulse ratio of the corrected clock signal (Rclk) and the corrected complementary clock signal (bRclk) for comparison with the required pulse ratio, e.g. via a phase detector (PD2) or frequency-phase detector. An independent claim for a clock signal pulse ratio correction method is also included.