Integrated circuit dynamic RAM device has PMOS transistors whose electrical resistances are varied in response to voltage levels of respective data lines

摘要

An active load circuit (230) has a pair of PMOS transistors (PL1,PL2) electrically connected between the data lines (GIO,GIOB) and the source voltages (VCC), respectively. The electrical resistances of the transistors are varied in response to the voltage levels of the respective data lines (GIO,GIOB). An Independent claim is also included for integrated circuit memory device operating method.