Integrated circuit e.g. delay locked loop integrated circuit for e.g. synchronous dynamic RAM, blocks periodic adjustment of delay, when excessive jitter is detected in external clock signal

摘要

A delay locked loop (DLL) control block connected to a delay line, periodically adjusts the delay in response to the external clock signal (CLK). The control block blocks the periodic adjustment of the delay, when excessive jitter is detected in the external clock signal. Independent claims are also included for the following: (1) DLL integrated circuit; (2) percent-of-clock delay circuit; and (3) method of operating DLL.