首页> 外国专利> DESIGN METHOD FOR PRINTED CIRCUIT BOARD, PLATED LEAD EVALUATION PROGRAM FOR REALIZING THIS DESIGN METHOD, EVALUATION DEVICE WITH COMPUTER-READABLE RECORDING MEDIUM RECORDING THIS PLATED LEAD EVALUATION PROGRAM, AND PRINTED CIRCUIT BOARD DESIGNED BY USE OF THIS DESIGN METHOD, PLATED LEAD EVALUATION PROGRAM OR EVALUATION DEVICE

DESIGN METHOD FOR PRINTED CIRCUIT BOARD, PLATED LEAD EVALUATION PROGRAM FOR REALIZING THIS DESIGN METHOD, EVALUATION DEVICE WITH COMPUTER-READABLE RECORDING MEDIUM RECORDING THIS PLATED LEAD EVALUATION PROGRAM, AND PRINTED CIRCUIT BOARD DESIGNED BY USE OF THIS DESIGN METHOD, PLATED LEAD EVALUATION PROGRAM OR EVALUATION DEVICE

机译:打印电路板的设计方法,用于实现该设计方法的平板式铅评估程序,具有计算机可读记录介质的评估装置,用于记录该平板式铅评估程序的评估设备以及通过使用此设计方法,平板式铅垫设计的印刷电路板设备

摘要

PROBLEM TO BE SOLVED: To provide a design method for a printed circuit board capable of contributing to improvement of reliability and quality of a product, to provide a plated lead evaluation program for realizing the design method, to provide an evaluation device with a computer-readable recording medium recording the plated lead evaluation program, and to provide the printed circuit board designed by use of the design method, plated lead evaluation program or evaluation device.;SOLUTION: This printed circuit board is obtained by executing: a process (step S1) for setting a value of conductive resistance of a plated lead electrically connecting a conductor to be plated and a plating current supply source on the basis of a design drawing of a drawing-around pattern of the plated lead; a process (step S2) for evaluating the value of the conductive resistance; a process (step S3) for deciding whether a laying-around path of the plated lead is incompatible or not, on the basis of an evaluation resu and a process (step 4) for changing the laying-around path of the plated lead when deciding that it is incompatible.;COPYRIGHT: (C)2005,JPO&NCIPI
机译:要解决的问题:提供一种印刷电路板的设计方法,该方法可以有助于提高产品的可靠性和质量,提供一种用于实现该设计方法的电镀引线评估程序,并为评估设备提供计算机,可读记录介质,记录镀覆铅评估程序,并提供通过使用该设计方法,镀覆铅评估程序或评估装置设计的印刷电路板;解决方案:该印刷电路板是通过执行以下步骤获得的: )用于基于镀覆引线的绕线图案的设计图来设置将待镀覆导体与镀覆电流供应源电连接的镀覆引线的导电电阻的值;评估导电电阻值的过程(步骤S2);根据评价结果,判断镀敷引线的绕线路径是否不相容的处理(步骤S3)。以及确定不兼容时改变镀覆铅的铺放路径的过程(步骤4)。版权所有:(C)2005,JPO&NCIPI

著录项

  • 公开/公告号JP2005215989A

    专利类型

  • 公开/公告日2005-08-11

    原文格式PDF

  • 申请/专利权人 SHARP CORP;

    申请/专利号JP20040021847

  • 发明设计人 UENO YUKIHIRO;

    申请日2004-01-29

  • 分类号G06F17/50;H05K3/00;H05K3/24;

  • 国家 JP

  • 入库时间 2022-08-21 22:37:00

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