Semiconductor memory device capable of accurate and stable operation

摘要

An external clock generating circuit generates a mode indicating signal at the “H” level and generates an external clock signal synchronized with a write command buffer signal, when a semiconductor memory device is not in an internal operation mode. When the semiconductor memory device enters an internal operation mode and the mode indicating signal makes a transition from “H” to “L”, the external clock signal is fixed at the “L” level. The external clock signal is not supplied to an external CUI, and the external CUI is set in a state in which reception of any external command is prohibited. Until the end of asynchronous reset, the mode indicating signal is kept at the “L” level, and thereafter raised to the “H” level, so that malfunction caused by an input of an external command during asynchronous reset period can be avoided.