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Computer system cache controller and methods of operation of a cache controller
Computer system cache controller and methods of operation of a cache controller
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机译:计算机系统高速缓存控制器和高速缓存控制器的操作方法
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摘要
In at least some embodiments, a computer system comprises a central processing unit (“CPU”), a bridge device coupled to a main memory, and a cache controller coupled between the bridge device and the CPU. The computer system further comprises a cache memory coupled to the cache controller and providing memory space to the CPU, wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using a first protocol and the bridge device communicates using a second protocol, and wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using the second protocol and the bridge device communicates using the first protocol.
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