首页> 外国专利> OP-AMP CONFIGURABLE IN A NON-INVERTING MODE WITH A CLOSED LOOP GAIN GREATER THAN ONE WITH OUTPUT VOLTAGE CORRECTION FOR A TIME VARYING VOLTAGE REFERENCE OF THE OP-AMP, AND A METHOD FOR CORRECTING THE OUTPUT VOLTAGE OF SUCH AN OP-AMP FOR A TIME VARYING VOLTAGE REFER

OP-AMP CONFIGURABLE IN A NON-INVERTING MODE WITH A CLOSED LOOP GAIN GREATER THAN ONE WITH OUTPUT VOLTAGE CORRECTION FOR A TIME VARYING VOLTAGE REFERENCE OF THE OP-AMP, AND A METHOD FOR CORRECTING THE OUTPUT VOLTAGE OF SUCH AN OP-AMP FOR A TIME VARYING VOLTAGE REFER

机译:闭环增益大于1且具有输出电压校正的非反相模式下的OP-AMP,可根据OP-AMP的时变电压基准进行校正,并且提供一种校正此类OP-AMP的输出电压的方法时变电压参考

摘要

A circuit (1) comprising eight DACs (2a to 2h), the analog outputs of which are applied to the non-inverting inputs (6) of corresponding op-amps (7a to 7h) for gaining up the analog output voltage from the corresponding DAC (2). The op-amps (7) are identical, and are configured in a non-inverting mode with a closed loop gain of two provided by first and second resistors (R1) and (R2). Primary outputs (8) of the op-amps (7) are coupled to output pins (9a to 9h) of the circuit (1). The second resistors (R2) couple primary inverting inputs (12) of the op-amps (7) to a common voltage reference rail (14), which is coupled to a true ground reference pin (15) through a coupling wire (16) which exhibit a combined inherent resistance (Rp). The voltage reference on the common voltage reference rail (14) varies with time as the output signals of the op-amps (7) vary, and would thus result in cross-talk between the DACs (2a to 2h). Each op-amp (7) comprises a secondary differential input amplifier stage (36), the non-inverting and inverting inputs (37,38) of which are coupled to the common voltage reference rail (14) and the ground reference pin (15), respectively. The secondary differential input stage (36) provides a secondary current to a node (29) in the op-amp (7) in response to variation in the time varying voltage reference for summing with an intermediate current provided through the node (29) by a primary differential input amplifier stage (25) of the op-amp (7) for correcting the output voltage signal on the primary output (8) for variation in the voltage reference on the common voltage reference rail (14).
机译:包含八个DAC( 2 a 2 h ,其模拟输出将应用于相应运算放大器( 7 a 的同相输入( 6 ) 7 h ),以从相应的DAC( 2 )获得模拟输出电压。运算放大器( 7 )相同,并配置为同相模式,其第一和第二电阻(R 1 )提供的两个闭环增益和(R 2 )。运算放大器( 7 )的主要输出( 8 )耦合到输出引脚( 9 a )到电路( 1 )的 9 h )。第二个电阻(R 2 )将运算放大器( 7 )的初级反相输入( 12 )耦合到公共参考电压轨( 14 ),其通过耦合线( 16 )耦合到真正的接地参考引脚( 15 ),该耦合线具有组合的固有电阻( R p )。随着运算放大器( 7 )的输出信号变化,公共参考电压轨( 14 )上的参考电压会随时间变化,因此会导致交叉DAC之间的对话( 2 a 2 h )。每个运算放大器( 7 )包括一个次级差分输入放大器级( 36 ),同相和反相输入( 37,38 )分别耦合到公共参考电压轨( 14 )和接地参考引脚( 15 )。次级差分输入级( 36 )为响应运算放大器( 7 )中的节点( 29 )提供次级电流。时变电压基准的变化,以与运算放大器的初级差分输入放大器级( 25 )通过节点( 29 )提供的中间电流相加( 7 ),用于校正主输出( 8 )上的输出电压信号,以改变公共参考电压轨( 14 )上的参考电压)。

著录项

  • 公开/公告号US2005122170A1

    专利类型

  • 公开/公告日2005-06-09

    原文格式PDF

  • 申请/专利权人 PATRICK C. KIRBY;

    申请/专利号US20030728053

  • 发明设计人 PATRICK C. KIRBY;

    申请日2003-12-04

  • 分类号H03F3/45;

  • 国家 US

  • 入库时间 2022-08-21 22:22:56

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号