首页> 外国专利> Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same

Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same

机译:可编程连接器/隔离器和采用掩埋触点的双多晶硅层CMOS工艺

摘要

An integrated circuit structure for MOS-type devices including a silicon substrate of a first conductivity type; a first gate insulating regions selectively placed over the silicon substrate of the first conductivity tape; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; a second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulated therefrom.
机译:一种用于MOS型器件的集成电路结构,包括第一导电类型的硅衬底;第一栅极绝缘区,选择性地放置在第一导电带的硅衬底上;第一多晶硅层,选择性地置于第一导电类型的硅衬底上;第二栅绝缘区,选择性地放置在第一栅绝缘区和第一多晶硅层上;第二多晶硅层,选择性地放置在第二栅极绝缘区域上;第二导电类型的第一掩埋硅区域,被掩埋在第一导电类型的硅衬底内,被放置在第一多晶硅层之下并与其接触;第二导电类型的第二掩埋硅区域,埋在第一导电类型的硅衬底内,位于第二栅极绝缘区域之下,第二多晶硅层之下并与其绝缘。

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