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Memory defect redress analysis treating method, and memory testing apparatus performing the method

机译:存储器缺陷补救分析处理方法以及执行该方法的存储器测试装置

摘要

There are provided a failure repair analyzing and processing method and a memory testing apparatus provided with a failure repair analyzing and processing apparatus using this method, that are capable of reducing a time duration required to perform the failure repair analysis and processing for a multi-bit memory having redundancy structure. A plurality of repair analysis units as well as a common failure analysis memory are provided, and these repair analysis units are concurrently operated in parallel with each other, thereby to carry out respective repair analyses and processings for failure memory cells of plural data bits read out from the failure analysis memory in the plural repair analysis units concurrently and in parallel with each other. As a result, a time duration required to execute the failure repair analysis and processing is shortened.
机译:提供了一种故障修复分析和处理方法以及具有使用该方法的故障修复分析和处理设备的存储器测试设备,其能够减少对多位执行故障修复分析和处理所需的时间。具有冗余结构的存储器。提供多个维修分析单元以及公共故障分析存储器,并且这些维修分析单元彼此并行地并行操作,从而对读取的多个数据位的故障存储单元进行相应的维修分析和处理。多个维修分析单元中的故障分析存储器中的故障信号来自并发地和并行地。结果,缩短了执行故障修复分析和处理所需的时间。

著录项

  • 公开/公告号US6907385B2

    专利类型

  • 公开/公告日2005-06-14

    原文格式PDF

  • 申请/专利权人 TAKAHIRO YASUI;

    申请/专利号US20030399082

  • 发明设计人 TAKAHIRO YASUI;

    申请日2001-10-19

  • 分类号G01R31/26;

  • 国家 US

  • 入库时间 2022-08-21 22:20:52

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