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Method of manufacturing the semiconductor device intended to prevent a leakage current from occuring due to a gate induced drain leakage effect
Method of manufacturing the semiconductor device intended to prevent a leakage current from occuring due to a gate induced drain leakage effect
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机译:旨在防止由于栅极感应的漏极泄漏效应而发生泄漏电流的半导体器件的制造方法
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摘要
A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.
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