DELAY LOCKED LOOP OF SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE, ESPECIALLY INCLUDING A CLOCK BUFFER CONTROL UNIT

摘要

Purpose: a delay lock loop of a synchronous semiconductor memory device is arranged to reduce unnecessary current consumption in an auto refresh mode. Construction: it includes the first and second clock buffers (31 that arithmetic register, which controls DLL (delay lock loop), 32), a clock divider (33), a phase comparator (39), a delay monitoring device, a delay model (42) and the first and second DLL drivers (40,41). Delay monitoring device also includes first and second and third delay line (34,35,36), a shift register (37), a shift controller (38), the first and second DLL drivers and a delay model. Register control DLL further comprises a clock buffer controller (53) to generate clock buffer control signal (buff_ctrl). Clock buffer controller receives an active signal, an automatic refresh signal and a clock enabling signal. Clock buffer controls signal and enables and disable the first and second clock buffers according to a mode of operation of device.