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Data output control circuit of a double data rate (DDR) synchronous semiconductor memory device responsive to a delay locked loop (DLL) clock
Data output control circuit of a double data rate (DDR) synchronous semiconductor memory device responsive to a delay locked loop (DLL) clock
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机译:响应延迟锁定环(DLL)时钟的双倍数据速率(DDR)同步半导体存储设备的数据输出控制电路
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摘要
A semiconductor memory device using system clock with a high frequency can maintain a constant margin of operation even with a changed operating environment including voltage level, temperature, and process. The semiconductor memory device includes a data output control circuit configured to control data outputted in synchronization with a falling edge of a system clock using a first output source signal corresponding to a rising edge of the system clock, and to control data outputted in synchronization with the rising edge of the system clock using a second output source signal corresponding to a falling edge of the system clock, and a data output circuit configured to output data, the data output circuit being controlled by the data output control circuit.
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