SEMICONDUCTOR MEMORY DEVICE HAVING ADDITIVE LATENCY, ESPECIALLY REDUCING SAME PATH OF ACTIVE LATENCY WHICH INPUTTED COMMAND HAS

摘要

PURPOSE: A semiconductor memory device having additive latency is provided to reduce the area of a circuit generating a CAS signal having additive. CONSTITUTION: The first command decoding unit(24) receives a buffered external command and generates a read/write command signal by detecting a read command and a write command. The second command decoding unit(11) outputs an internal command signal by receiving the buffered external command, and generates a CAS latency enable signal by judging whether the applied command is a write command or a read command. The first delay unit(21) delays the read/write command signal as much as delay time corresponding to additive latency. The second delay unit(23) generates a write CAS signal by delaying an output signal of the first delay unit as much as delay time corresponding to CAS latency. And a switching unit(22) outputs the output signal of the first delay unit as a read CAS signal or transfers it to the second delay unit in response to the CAS latency enable signal.