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DATA INVERSION CIRCUIT OF SEMICONDUCTOR DEVICE FOR PERFORMING INVERSION OPERATION BASED ON THE INTERVAL FOR READING DATA AND DATA INVERSION METHOD USING THE SAME
DATA INVERSION CIRCUIT OF SEMICONDUCTOR DEVICE FOR PERFORMING INVERSION OPERATION BASED ON THE INTERVAL FOR READING DATA AND DATA INVERSION METHOD USING THE SAME
An integrated circuit device includes a data inversion circuit configured to support an inversion mode of operation. The inversion mode of operation inverts selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof. The data inversion circuit is further configured to support a bypass mode of operation. The bypass mode of operation disables inversion of a second one of the plurality of N-bit words when a delay between receipt of the second one of the plurality of N-bit words and receipt of an immediately preceding first one of the plurality of N-bit words is greater than a predetermined time interval. Related methods are also discussed.
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