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Method for generating net-list for integrated circuit device design

机译:用于集成电路器件设计的生成网表的方法

摘要

A method of generating a net-list for designing an integrated circuit device is provided, including generating a pin template file by laying out logic elements included in the integrated circuit device, generating a pin file by assigning a serial number to the logic elements and setting power names necessary for operating the logic elements, and generating a power inform template file by grouping an internal circuit of the integrated circuit device by a unit of power, generating a power inform file by combining the pin file with the power inform template file and arranging power information which is separately applied to each logic element, generating a final power inform file by assigning correct power names to power ports, to which power applied thereto is not defined, and completing a final net-list by combining core-related information of the integrated circuit device with the final power inform file.
机译:提供了一种生成用于设计集成电路器件的网表的方法,该方法包括:通过布置集成电路器件中包括的逻辑元件来生成引脚模板文件,通过向逻辑元件分配序列号并设置来生成引脚文件。操作逻辑元件所需的电源名称,并通过按电源单位对集成电路设备的内部电路进行分组来生成电源通知模板文件,通过将引脚文件与电源通知模板文件组合并生成电源通知文件来进行排列分别应用于每个逻辑元素的电源信息,通过为未定义所施加电源的电源端口分配正确的电源名称来生成最终电源通知文件,并通过组合电源的核心相关信息来完成最终网表具有最终功率通知文件的集成电路器件。

著录项

  • 公开/公告号KR100486274B1

    专利类型

  • 公开/公告日2005-04-29

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20020065247

  • 申请日2002-10-24

  • 分类号G06F17/50;

  • 国家 KR

  • 入库时间 2022-08-21 22:03:54

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