DSP having wide memory bandwidth and DSP memory mapping method

摘要

This DSP architecture and its memory mapping method has a large memory bandwidth is disclosed. DSP architecture of the present invention in a first, second and third memory elements and the second row direction below the first row direction of the DSP architecture that connects with the first communication port arranged in a first row direction of the DSP architecture arranged and connected to the fourth memory elements, processing elements, and a fifth memory element and, and the first communication port, and includes the sixth, seventh and eighth memory elements arranged in a third row direction of the DSP architecture. Processing elements are interconnected to the first through eighth memory element. DSP architectures by placing the processing elements in the center constitutes the first through eighth memory element to one array unit devices are connected to the processing elements, the array unit elements are arranged in the row direction and the column direction of the DSP architecture. Thus, according to the present invention, the data since it has a wide data bandwidth between the processing elements and memory elements of the DSP, it is possible to reduce the memory access count when data processing with a higher data concentrator (data rate), such as a high resolution video it is suitable for processing.