首页> 外国专利> device for measuring u0431u0430u0440u043eu043cu0435u0442u0440u0438u0447u0435u0441u043au0438u0445 vertical speed and height and static air pressure at the altitude of flight aircraft

device for measuring u0431u0430u0440u043eu043cu0435u0442u0440u0438u0447u0435u0441u043au0438u0445 vertical speed and height and static air pressure at the altitude of flight aircraft

机译:在飞行器高度上用于测量 u0431 u0430 u0440 u043e u043c u0435 u0442 u0440 u0438 u0447 u0435 u0441 u0431 u043a u0438 u0445的垂直速度和高度以及静态气压的设备

摘要

the device u0434u043bu00a0 u0438u0437u043cu0435u0440u0435u043du0438u00a0 u0431u0430u0440u043eu043cu0435u0442u0440u0438u0447u0435u0441u043au0438u0445 vertical speed and altitude, and static u0434u0430u0432u043bu0435u043du0438u00a0 air at an altitude of flight, the plane containing the u0431u0430u0440u043eu0432u044bu0441u043eu0442u043eu043cu0435u0440, with u0441u0442u043eu00a0u0449u0438u0439 of consecutively united's successor, air pressure, air u0434u0430u0432u043bu0435u043du0438u00a0 pipeline sensor static and functional u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0 and s u0438u043bu044cu0442u0440, u0441u043eu0441u0442u043eu00a0u0449u0438u0439 of u043fu00a0u0442u0438 amplifiers, three u0441u0443u043cu043cu0430u0442u043eu0440u043eu0432,the six elements of the delay and the four u0432u044bu0447u0438u0442u0430u0442u0435u043bu0435u0439, in this way u0431u0430u0440u043eu0432u044bu0441u043eu0442u043eu043cu0435u0440u0430 is connected to the first gate through the first u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0 and consistently the pe u0440u0432u044bu0439, second and third elements of the second door, and through the first element delay to the first entrance and through the first series and the wto roy elements delayed second by second u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0,both u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0 their outputs are connected through the first adder and consistently united with him the first amplifier and the fourth element of the delay to the first the third u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0 mu, output of which is connected to the first gate through the second amplifier and a third amplifier 3 through the first entrance of the second u0441u0443u043cu043cu0430u0442u043eu0440u0430, the exit of which is connected with the u043fu043eu0442u0440u0435u0431u0438u0442u0435u043bu00a0u043cu0438 informationin u043fu00a0u0442u044bu0439 element delays with his second entrance and the second entrance of the third u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0, exit the fourth u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0 through the fourth amplifier is connected to the third in the second, and through them u043fu00a0u0442u044bu0439 amplifier with the second the third u0441u0443u043cu043cu0430u0442u043eu0440u0430 entrance, exit which is connected with the u043fu043eu0442u0440u0435u0431u0438u0442u0435u043bu00a0u043cu0438 information through the sixth element delays with his third place u043eu0442u043bu0438u0447u0430u044eu0449u0435u0435u0441u00a0 whatin order to u0443u043cu0435u043du044cu0448u0435u043du0438u00a0 errors u0438u0437u043cu0435u0440u0435u043du0438u00a0 through compensation for u0437u0430u043fu0430u0437u0434u044bu0432u0430u043du0438u00a0 signal in u043fu043du0435u0432u043cu043eu0442u0440u0430u043au0442u0435 u0431u0430u0440u043eu0432u044bu0441u043eu0442u043eu043cu0435u0440u0430, he added three u0441u0443u043cu043cu0430u0442u043eu0440u0430, ced u044cu043cu043eu0439 element delay, two u0443u043cu043du043eu0436u0438u0442u0435u043bu00a0, four u0443u0441u0438u043bu0438u0442u0435u043bu00a0, u043fu043eu0441u0442u043eu00a0u043du043du043eu0435 storage device and two u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0, exit is connected with the first gate u043fu00a0u0442u043eu0433 u0431u0430u0440u043eu0432u044bu0441u043eu0442u043eu043cu0435u0440u0430 on the u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0,the second input of which is connected to the third u0441u0443u043cu043cu0430u0442u043eu0440u0430 u0443u043fu0440u0430u0432u043bu00a0u044eu0449u0435u043cu0443 between exit and entrance u043fu043eu0441u0442u043eu00a0u043du043du043eu0433u043e mass storage devices, and output to the first the first u0443u043cu043du043eu0436u0438u0442u0435u043bu00a0, second input which is connected to the gate u043fu043eu0441u0442u043eu00a0u043du043du043eu0433u043e mass storage devices, and output to the first entrance of the fourth u0441u0443u043cu043cu0430u0442u043eu0440u0430, u0441u043eu0435u0434u0438u043du0435u043du043d wow my second entrance to exit sensor static u0434u0430u0432u043bu0435u043du0438u00a0 airin this way the fourth u0441u0443u043cu043cu0430u0442u043eu0440u0430 is connected with u043fu043eu0442u0440u0435u0431u0438u0442u0435u043bu00a0u043cu0438 information through the sixth amplifier with first and second u0443u043cu043du043eu0436u0438u0442u0435u043bu00a0 entrance, the second input of which u0441u043eu0435u0434u0438u043d yong an sixth u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0 and exit from the first entrance u043fu00a0u0442u043eu0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430, gate which is connected to the first entrance and the second entrance to the sixth u0441u0443u043cu043cu0430u0442u043eu0440u0430 u0447u0435u0442u0432u0435u0440u0442u043eu0433 on the u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0, first entrance which is connected with the outlet u0431u0430u0440u043eu0432u044bu0441u043eu0442u043eu043cu0435u0440u0430,and exit through the seventh amplifier with the second entrance of the sixth u0441u0443u043cu043cu0430u0442u043eu0440u0430, united with my third entrance in the eighth amplifier connected to the third u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0 and you the second through seventh element delays in entrance u043fu00a0u0442u043eu0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430 and with the first entrance of the sixth u0432u044bu0447u0438u0442u0430u0442u0435u043bu00a0, second input which is connected to the exit of u044du043bu0435u043cu0435 u043du0442u0430 delaysand the outlet u043fu00a0u0442u043eu0433u043e element delays in u0434u0435u0432u00a0u0442u044bu0439 amplifier is connected to the fourth the third u0441u0443u043cu043cu0430u0442u043eu0440u0430.
机译:设备 u0434 u043b u00a0 u0438 u0437 u043c u0435 u0440 u0435 u043d u043d u0438 u00a0 u0431 u0430 u0440 u043e u043c u0435 u0435 u0442 u0440 u0438 u0447 u0435 u043a u0438 u0445垂直速度和海拔高度,以及静态 u0434 u0430 u0432 u043b u0435 u043d u043d u0438 u00a0处于飞行高度的空气,该飞机包含 u0431 u0430 u0440 u0440 u043e u0432 u044b u0441 u043e u0442 u043e u043c u0435 u0440,以及连续联合后继者的 u0441 u0442 u043e u00a0 u0449 u0438 u0439,气压,空气 u0434 u0430 u0432 u043b u0435 u043d u0438 u00a0管道传感器静态和功能性 u043f u0440 u0435 u043e u043e u0431 u0440 u0430 u0437 u043e u0432 u0430 u0442 u0435 u043b u00ac和s u0438 u043b u044c u043f u00a0 u0442 u0438的 u0442 u0440, u0441 u043e u0441 u0442 u043e u00a0 u0449 u0438 u0438,三个uu1,u0441 u0443 u043c u043c u0430 u0442 u04e u0440 u043e u0432,这六个延迟元素和四个 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0435 u043b u0435 u0439方式 u0431 u0430 u0440 u043e u0432 u044b u0441 u043e u0442 u043e u043c u0435 u0440 u0430通过第一个 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0435 u043b u00a0,并且始终是pe u0440 u0432 u044b u0439,第二扇门的第二个和第三个元素,并通过第一个元素延迟到第一个入口,并通过第一个序列和wto roy元素每秒延迟 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0435 u043b u00a0,两者 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0442 u0435 u043b u043b u00a0通过第一个加法器,并与他始终如一地结合在一起,将第一个放大器和延迟的第四个元素连到第一个,第三个 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0435 u043b u00b0 whi的出口通过第二个放大器连接到第一栅极,并通过第二个放大器的第一个入口连接到第三个放大器3。 ch与 u043f u043e u0442 u0440 u0435 u0431 u0438 u0442 u0435 u043b u00a0 u043c u0438中的信息连接时,元素会因第二次进入而延迟,并且第三个 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0435 u043b u00a0的第二个入口,退出第四个 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0432 u0435 u043b u00b0第四个放大器与第二个放大器相连,第二个则通过它们与第二个放大器相连,第三个 u0441 u0443 u043c u043c u0430 u0442 u043e u0440 u0430入口,通过第六个元素与 u043f u043e u0442 u0440 u0435 u0431 u0438 u0442 u0435 u043b u00a0 u043c u0438信息连接的出口,其第三位 u043e u0442 u043b u0438 u0447 u0430 u044e u0449 u0435 u0435 u0441 u00a0顺序为 u0443 u043c u0435 u043d u044c u0448 u0435 u043d u0438 u00a0错误 u0438 u0437 u043c u043c u0440 u0435 u043d u0438 u00a0通过对 u0437 u0430 u043f u0430 u0437 u0434 u044b u0432 u0430 u043d u0435 u0432 u043c u043e u0442 u0440 u0430 u043a u0442 u043e u0431 u0430 u0440 u043e u0432 u044b u0441 u043e u0442 u043e u043c u0435 u0440 u0430,他添加了三个 u0441 u0443 u043c u043c u043c u0430 u0442 u043e u0440 u0430, ced u044c u043c u043e u0439元素延迟,两个 u0443 u043c u043d u043e u0436 u0438 u0442 u0435 u043b u00a0,四个 u0443 u0441 u0438 u043b u0438 u0442 u0435 u043b u00a0, u043f u043e u0441 u0442 u043e u00a0 u043d u043d u043e u0435存储设备和两个 u0432 u044b u0447 u0438 u0442 u042 u0430 u0442 u0435 u043b u00a0,与 u0432 u044b上的第一个门 u043f u00a0 u0442 u043e u0433 u0431 u0430 u0440 u043e u0432 u044b u0441 u0441 u043e u0442 u043e u043c u043c u0435 u0435 u0440 u0430 u0447 u0438 u0442 u0430 u0442 u0435 u043b u00a0,其第二个输入连接到第三个 u0441 u0443 u043c u043c u0430 u0442 u043e u0440 u0430 u0443 u043f u0440 u0430 u0432 u043b u00a0 u044e u0449 u0435 u043c u0443在出口和入口之间 u043f u043e u0441 u0442 u043e u00a0 u043d u043d u043d u043e u0433 u043e大容量存储设备,并输出到第一个第一个 u0443 u043c u043d u043e u0436 u0438 u0442 u0435 u043b u00a0,第二个输入连接到门 u043f u043e u0441 u0442 u043e u00a0 u043d u043d u043d u043e u0433 u043e设备,并输出到第四个 u0441 u0443 u043c u043c u0430 u0442 u043e u0440 u0430, u0441 u043e u0435 u0434 u0434 u0438 u043d u0435 u043d u043d第二个出口到出口传感器静态 u0434 u0430 u0432 u043b u0435 u043d u0438 u00a0这样,第四个 u0441 u0443 u043c u043c u0430 u0442 u043e u043e u0440 u0430与 u043f连接 u043e u0442 u0440 u0435 u0431 u0438 u0442 u0435 u043b u00a0 u043c u0438信息通过第六放大器带有第一和第二 u0443 u043c u043d u043e u0436 u0438 u0442 u0435 u043b u00a0入口,其中第二个输入 u0441 u043e u0435 u0434 u0438 u043d是第六个 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0435 u043b u00a0并从第一个入口 u043f 退出u00a0 u0442 u043e u0433 u043e u0441 u0443 u043c u043c u0430 u0442 u043e u0440 u0430,与第一个入口和第二个入口相连的门与第六个 u0441 u0443 u043c u0432 u044b u0447 u0447 u0438 u0442 u0430 u0442 u0435 u0432 u0432 u0432 u0432 u0435 u0440 u0442 u043e u0433中的u043c u0430 u0442 u0435 u00a0,与插座 u0431 u0430 u0440 u043e u0432 u043b u044b u0441 u043e u0442 u043e u043c u043c u0435 u0440 u0430连接的第一个入口,然后通过第七个放大器从第二个入口进入第六个 u0441 u0443 u043c u043c u0430 u0442 u043e u0440 u0430,与我的第八个入口中的第三个入口相连,该放大器连接到第三个 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0435 u043b u00a0,您进入入口的第二到第七个元素会延迟 u04 3f u00a0 u0442 u043e u0433 u043e u0441 u0443 u043c u043c u0430 u0442 u043e u0440 u0430和第六个 u0432 u044b u0447 u0438 u0442 u0430 u0442 u0435 u043b u00a0,第二个输入连接到 u044d u043b u0435 u043c u0435 u043d u0442 u0430的出口和插座 u043f u00a0 u0442 u0432 u043e u0433 u043e的元素延迟在 u0434 u0435 u0432 u00a0 u0442 u044b u0439中,放大器连接到第四,第三 u0441 u0443 u043c u043c u0430 u0442 u043e u0440 u0430。

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