Dynamic RAM storage device for row-cycle time and read latency in semiconductors has a cell field with multiple memory cells, a control device and an electrical bias

摘要

A write cycle has a stage (CHARGE) for writing data into memory cell capacitors so that a minimum row-cycle time (tRC) is produced for a write command (WR) for the row-cycle time. A control device can be designed so that a minimum write command row-cycle time (tRC(WR)) is equal to a minimum destructive read command row-cycle time (tRC(DRD)). An independent claim is also included for a method for reading data from, and writing data to, memory cells in a dynamic RAM device.