Charge trapping memory cell used as transistor comprises semiconductor body or substrate having upper side with curve in channel region

摘要

A charge trapping memory cell comprises a semiconductor body (1) or substrate having an upper side with a curve in the channel region. The curve is structured so that channel width measured across the connection line between source/drain regions and delimited by STI insulations is larger compared with a planar structure of the channel width. The curve is at least two thirds of the channel width.