fehlererfassungsverfahren and system r amp; t.; r processors, the verriegelungsschrittweise concurrent subprocesses used.

摘要

athe processor, in order for the exp exp &; hrungsarchitektur and professional; of;at least two orders per cycle (e.g. 2n orders percycle processes, where n is an integer gr & all, & white, or equal to one) andat least two symmetrical exp & t.; hrungseinheitenincludes. the processor includes a befehlsabrufeinheit to retrieveorder of n (where n is an integer gr & all, & white, or equal to one) anda befehlsdecodierer to decode the n orders. the fehlererfassungsmechanismusincludes duplizierungshardware to duplicate the n orders in athe first b & professional; traden commands, and a second b & professional; traden orders. a first variant hrungseinheit and professional;the variant & t.; preparationthe first b & t.; ndels ofcommands in a first variant hrungszyklus and professional;and a second symmetrical exp & t.; hrungseinheit to exp and professional; of;second c & t.; ndelscommands in the first bo & t.; hrungszyklusare planned. the fehlererfassungsmechanismus also includesvergleichshardware to compare the results of the first variant and professional; hrungseinheit andthe results of the second variant and professional; hrungseinheit.the vergleichshardware can ausnahmeeinheit to create aexceptions include (e.g. detect an error when the resultsare not the same. a festschreibeinheit is envisaged to establishone of the results when the results are the same.