A sense amplifier (1) for use in memory devices. The sense amplifier (1) may include a pair of cross-coupled inverters (2A,2B), each inverter including at least two transistors (4,5). The sense amplifier (1) may further include a first capacitor (10) coupled to a first input/output terminal (BLC) of the sense amplifier (1) and a second capacitor (11) coupled to a second input/output terminal (BLT) thereof. A change in voltage differential appearing across the input/output terminals (BLC,BLT) bootstraps the cross-coupled inverters (2A,2B) to facilitate activation and deactivation of the transistors (4,5) in the cross-coupled inverters (2A;2B). Consequently, response time of the sense amplifier (1) is reduced. IMAGE
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