Determining wire capacitance for a VLSI circuit

摘要

A method (200) and system 100 for determining wire capacitance for a VLSI circuit design 109, (300), (202). All hierarchical blocks (inv1, inv2) of a portion of the design are determined; Indicia of the most accurate one of a plurality of wire capacitance data sources 110 are stored for a plurality of blocks (205). A wire capacitance database 112 is generated (210) with an entry for each net in at least a plurality of the blocks, using information stored in one of the wire capacitance data sources 110; Further a hierarchical connectivity model is generated for the design 109, (300). The hierarchical connectivity model and said wire capacitance database 112 are used to determine a cumulative wire capacitance value 114 for each HLSN in each of the blocks in a portion of the design to be analyzed.