HIGH RELIABILITY TRIPLE REDUNDANT LATCH WITH INTEGRATED TEST FACILITY

摘要

PROBLEM TO BE SOLVED: To reduce a soft error incidence rate of a triple redundant latch.;SOLUTION: A circuit and a method of this high reliability triple redundant latch with integrated testability are provided in a preferred embodiment. The identical logical value is set into each settable memory element of three settable memory elements. After setting the settable memory elements, a voting structure having inputs from the second settable memory element and the third settable memory element, for controlling the settable memory elements determine the logical value held on the first settable memory element. Data can be scanned into and out in both directions relative to the second settable memory element. The data are propagated up to the second settable memory element through a buffer. The data can be scanned out from the triple redundant latch by using the third settable memory element. A propagation delay through a latch is the only propagation delay of the triple redundant latch.;COPYRIGHT: (C)2006,JPO&NCIPI